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VHDPlus IDE Changelog

  • Fix CYC5000 Long Term programming

  • Add CYC5000 GUI
  • Fix Generic Code generation

  • Add Insert Key functionality
  • Fix Auto signal connection

  • Fix VHDP Support throwing wrong exceptions for using Record types inside ParFor Loops
  • Sync Output/Serial Monitor Font Size with Editor

  • Correct wrong default value for GHDL Options

  • Add SimulationOptions for GHDL allowing to add e.g. --stop-sim arguments
  • Fix not being able to type spaces in settings
  • Give clearer message when GTKWave fails to start

  • Add tooltip to description in errorlist
  • New Verilog/Systemverilog package

  • Fix infinite loop while importing an existing folder into itself
  • Projects will now exclude files that failed to load while compiling

  • Fix ModelSim Path detection

  • Add VHDP component completion for VHDL
  • Fix changing themes on Windows
  • Slightly improved startup time
  • Fix removing/updating library packages (Windows only)

  • Fix crash on startup trying to load light/superdark theme

  • Fix terminal on Linux
  • Fix freeze when creating projects on Windows
  • Fix string converter
  • Fix mousewheel scrolling inside dropdown menus

  • Fix Modelsim for Linux
  • Add GHDP creation for VHDL and Verilog
  • Fix a possible crash on Undo/Redo operations

  • Fix serial monitor options
  • Drastically improve project load times

  • Fix pin order after disconnecting connections
  • Fix crash while editing files outside of projects
  • Fix using .vhdl files

  • Generate templates with vhdl
  • Fix crash on deleting arduino sketches
  • Prevent loading the same project twice


  • Fix long term programming for CYC1000

  • Fix possible rendering crash while resizing

  • Fix Modelsim simulation with GHDP
  • Fix backup system in case IDE crashes
  • Added border to floating tools on linux/macos to prevent buggy drag behaviour
  • Fix selection scrolling in editview

  • Fixed signal I/O creation in some cases
  • Improved dark terminal colors in dark mode
  • Fix NIOS Debugging on Linux

  • Fix broken programmer
  • Fix serial monitor negative baudrate crash
  • Fix NIOS bsp generation

Breaking ⚠️

This update changes the way settings are loaded. This means your current settings may be lost. This is a one time change that had to be done before 1.0, sorry 🥲. Some packages may have to be reinstalled too in order to set their paths again.


This update adds the option to use the GHW file format with GHDL. This increases simulation speed by almost 50%, but requires GTKWave to run. It can be activated with Settings -> Use GTKWave and Settings -> Use GHDL GHW after installing GTKWave.

Other changes

  • Added option to restore package paths
  • Internal refactorings
  • Fixed operator correction in certain situations

  • Correct wrong cruvi LS definitions on Max10 boards
  • Fix saving in create window
  • Add error on missing components

  • Fix missing cruvi extension views

  • Fix errorlist style and sorting
  • Drastically improved performance on files with lots of errors
  • Fixed a possible crash

  • Fix button visibility if no project is open
  • Hint when trying to open new project in Quartus
  • Fix possible crash

New Toolbar Design

We simplified the design to make it more minimalistic. This way the IDE should feel more familiar for beginners. Shortcuts, to control Arduino or NIOS CPUs are only shown when you really need them. This change is still experimental and we expect to improve it in future releases.

If you find any bugs or need help, please join our Discord!


  • Huge performance improvements
  • Fix IO Voltage not set in new projects
  • Fix fullscreen glitches after minimizing
  • Fix folding in line comments
  • Fix long term programming for official hardware
  • Fix detecting external file changes
  • Fix cyc1000 and max1000 16k pin definitions
  • VHDP support improvements
  • Fix image viewer for linux/macos
  • Fix NIOS Debugger on quartus 18


  • Huge performance improvements
  • Make Verilog and Systemverilog support more usable (still bad though :/ )
  • Hundreds of small changes and improvements

We are getting closer to the 1.0 release. To get an update on our current situation and future plans, please read our blog!

  • Fix wrong max1000 cruvi pin definition
  • Fix resolving array declarations of externally defined record types
  • Fix vhdl / verilog component detection
  • Allow adding libraries as shared files

  • Fix GHDP
  • Fix declaration of Function overloads
  • Check for correct function return types
  • Fix declaration of multiple variables using ,

  • Linux / MacOS hotfix

  • Fix VHDP Package support
  • Add missing types / functions
  • Fix VHDL / Verilog component auto signal creation
  • Fix shared files
  • Added option to exclude files from quartus compilation
  • Fix auto operator after AND
  • Working functions in packages
  • Improved checks for declarations
  • Hugely improved type checks
  • Changed highlighting for functions

  • Fix max1000 and cyc1000 gui

  • Lots of small VHDP Language support improvements
  • Legend for graphical I/O connection
  • Improved Scrollbar hints (Show search results)
  • Connections can now use ';' instead of ','
  • Performance improvements

  • Fix permission issue that prevented loading FPGAs

  • [BREAKING] Changed the way to load FPGAs
  • Analyzer and Language support fixes fixes
  • Better handling of subtypes
  • Code completion after operators
  • Fix highlighting

  • Fix operator correction for signals

  • Fix a breaking bug using the Shield with extensions

  • Fix some issues with automatic signal generation
  • Updated description for Wait
  • Linux/MacOS compatibility fixes

  • Fix serial monitor not changing baud rate without refresh (Linux only)

  • Fix missing library on some distros

  • Improve readability for terminal in lightmode (darker colors)
  • Fix VHDL formatting for "else generate"
  • Create arduino project automatically when selecting WiFi extension

  • Fix invisible simulator byteblocks

  • Improved hover information for VHDP
  • Fixed an issue where generated VHDL files were used like normal project files
  • Fixed issues with CLRF line endings
  • Minor style fixes

  • Fixed some issues with auto indent for VHDL
  • Minor style changes
  • Small performance improvements

VHDP Analyzer

  • Fixed a possible crash for huge files
  • Improved Segment Check
  • Added Subtype


  • New, cleaned up and futureproof .vhdpproj format.
  • Fixed failing Arrow USB Driver installation on some Linux distros
  • Fixed a bug where the Team Explorer failed to produce a comparison
  • Reduced Package Manager lag while extracting packages
  • Drastically improved editor initialization time
  • Improved editor performance
  • Fixed Quartus Project import (Linux only hotfix)

  • Added a workaround for some Linux distros having trouble loading system fonts.

  • Added built-in changelog
  • Improved completion speed