VHDL Setup and Simulation
Requirements
Version | Information | |
---|---|---|
VHDPlus IDE | 0.9+ | Instructions |
Packages | - | GHDL or ModelSim |
Video Tutorial
Written tutorial
Setup
- (Optional) Open
Extras > Package manager
and install the VHDL Language Support - (Optional) Open
Extras > Settings > Editor
and select what support you want to use
You can click on File > Import Quartus Project
to import an existing VHDL project
Create a VHDL project
- Create a new project and select
VHDL Project with Simulation
. An example for a blinking LED will be created.
blink: process(clk)
begin
if rising_edge(clk) then
if counter < 1000000 then
counter <= counter + 1;
else
counter <= 0;
LED <= NOT LED;
end if;
end if;
end process blink;
- A testbench file will be created where the clock signal is simulated. An instance of the blink code is created and simulated.
clk_proc: process
begin
while finished /= '1' loop
CLK <= '0';
wait for period_time/2;
CLK <= '1';
wait for period_time/2;
end loop;
wait;
end process clk_proc;
u1: Demo
port map
(
CLK => CLK,
LED => LED
);
Here you can find more information on creating testbenches for you VHDL code
Start the simulation
- Do a right click on the testbench file and select
Simulate with GHDL
orSimulate with Modelsim
- Check for errors in the output window
For GHDL:
- After GTK Wave is open, click on the component of which you want to see the signal
- Double click the signal to display in the wave window
- You can zoom out and see the simulated behavior
For Modelsim:
- After Modelsim is open, right click the signal to simulate and click on
Add to Wave
. Or you can just drag an drop the signals. - Select the
Run Length
and run the simulation with the buttons on top - You can zoom out and see the simulated behavior
Done ✔ Need help?
If everything worked as planned, the LED of your FPGA should blink every second.
If anything went wrong, feel free to ask for help.
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